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nazhishiyishunjiandeshi£¬dengsuozixingguolai£¬tazhengpazaiyigerenshenshang¡£nagerenjingjingdiwozaitadeshenxiashi£¬jiuxianglushangdeyikuaishitou¡£genlaohanxueUbuntu Server 2204-gcczhilingbangzhushoucedi16xiaojieyuanchuang2022-12-08 07:55¡¤hanlaoshishuoyunjisuancaozuoxitongxinxiruxia¡£root@hanyw:~# lsb_release -aNo LSB modules are available.Distributor ID: UbuntuDescription: Ubuntu 22.04.1 LTSRelease: 22.04Codename: jammyroot@hanyw:~# root@hanyw:~# uname -r5.15.0-53-genericGCCbangzhushoucededi16xiaojie£¬di9288~10288xing£¬ruxia¡£9288 This option provides a seed that GCC uses in place of random numbers in generating certain symbol names9289 that have to be different in every compiled file. It is also used to place unique stamps in coverage data9290 files and the object files that produce them. You can use the -frandom-seed option to produce reproducibly9291 identical object files.9292 The string can either be a number (decimal, octal or hex) or an arbitrary string (in which case it's9293 converted to a number by computing CRC32).9294 The string should be different for every file you compile.9295 -save-temps9296 Store the usual "temporary" intermediate files permanently; name them as auxiliary output files, as9297 specified described under -dumpbase and -dumpdir.9298 When used in combination with the -x command-line option, -save-temps is sensible enough to avoid9299 overwriting an input source file with the same extension as an intermediate file. The corresponding9300 intermediate file may be obtained by renaming the source file before using -save-temps.9301 -save-temps=cwd9302 Equivalent to -save-temps -dumpdir ./.9303 -save-temps=obj9304 Equivalent to -save-temps -dumpdir outdir/, where outdir/ is the directory of the output file specified9305 after the -o option, including any directory separators. If the -o option is not used, the -save-temps=obj9306 switch behaves like -save-temps=cwd.9307 -time[=file]9308 Report the CPU time taken by each subprocess in the compilation sequence. For C source files, this is the9309 compiler proper and assembler (plus the linker if linking is done).9310 Without the specification of an output file, the output looks like this:9311 # cc1 0.12 0.019312 # as 0.00 0.019313 The first number on each line is the "user time", that is time spent executing the program itself. The9314 second number is "system time", time spent executing operating system routines on behalf of the program.9315 Both numbers are in seconds.9316 With the specification of an output file, the output is appended to the named file, and it looks like this:9317 0.12 0.01 cc1 9318 0.00 0.01 as 9319 The "user time" and the "system time" are moved before the program name, and the options passed to the9320 program are displayed, so that one can later tell what file was being compiled, and with which options.9321 -fdump-final-insns[=file]9322 Dump the final internal representation (RTL) to file. If the optional argument is omitted (or if file is9323 "."), the name of the dump file is determined by appending ".gkd" to the dump base name, see -dumpbase.9324 -fcompare-debug[=opts]9325 If no error occurs during compilation, run the compiler a second time, adding opts and9326 -fcompare-debug-second to the arguments passed to the second compilation. Dump the final internal9327 representation in both compilations, and print an error if they differ.9328 If the equal sign is omitted, the default -gtoggle is used.9329 The environment variable GCC_COMPARE_DEBUG, if defined, non-empty and nonzero, implicitly enables9330 -fcompare-debug. If GCC_COMPARE_DEBUG is defined to a string starting with a dash, then it is used for9331 opts, otherwise the default -gtoggle is used.9332 -fcompare-debug=, with the equal sign but without opts, is equivalent to -fno-compare-debug, which disables9333 the dumping of the final representation and the second compilation, preventing even GCC_COMPARE_DEBUG from9334 taking effect.9335 To verify full coverage during -fcompare-debug testing, set GCC_COMPARE_DEBUG to say9336 -fcompare-debug-not-overridden, which GCC rejects as an invalid option in any actual compilation (rather9337 than preprocessing, assembly or linking). To get just a warning, setting GCC_COMPARE_DEBUG to9338 -w%n-fcompare-debug not overridden will do.9339 -fcompare-debug-second9340 This option is implicitly passed to the compiler for the second compilation requested by -fcompare-debug,9341 along with options to silence warnings, and omitting other options that would cause the compiler to produce9342 output to files or to standard output as a side effect. Dump files and preserved temporary files are9343 renamed so as to contain the ".gk" additional extension during the second compilation, to avoid overwriting9344 those generated by the first.9345 When this option is passed to the compiler driver, it causes the first compilation to be skipped, which9346 makes it useful for little other than debugging the compiler proper.9347 -gtoggle9348 Turn off generation of debug info, if leaving out this option generates it, or turn it on at level 29349 otherwise. The position of this argument in the command line does not matter; it takes effect after all9350 other options are processed, and it does so only once, no matter how many times it is given. This is9351 mainly intended to be used with -fcompare-debug.9352 -fvar-tracking-assignments-toggle9353 Toggle -fvar-tracking-assignments, in the same way that -gtoggle toggles -g.9354 -Q Makes the compiler print out each function name as it is compiled, and print some statistics about each9355 pass when it finishes.9356 -ftime-report9357 Makes the compiler print some statistics about the time consumed by each pass when it finishes.9358 -ftime-report-details9359 Record the time consumed by infrastructure parts separately for each pass.9360 -fira-verbose=n9361 Control the verbosity of the dump file for the integrated register allocator. The default value is 5. If9362 the value n is greater or equal to 10, the dump output is sent to stderr using the same format as n minus9363 10.9364 -flto-report9365 Prints a report with internal details on the workings of the link-time optimizer. The contents of this9366 report vary from version to version. It is meant to be useful to GCC developers when processing object9367 files in LTO mode (via -flto).9368 Disabled by default.9369 -flto-report-wpa9370 Like -flto-report, but only print for the WPA phase of link-time optimization.9371 -fmem-report9372 Makes the compiler print some statistics about permanent memory allocation when it finishes.9373 -fmem-report-wpa9374 Makes the compiler print some statistics about permanent memory allocation for the WPA phase only.9375 -fpre-ipa-mem-report9376 -fpost-ipa-mem-report9377 Makes the compiler print some statistics about permanent memory allocation before or after interprocedural9378 optimization.9379 -fprofile-report9380 Makes the compiler print some statistics about consistency of the (estimated) profile and effect of9381 individual passes.9382 -fstack-usage9383 Makes the compiler output stack usage information for the program, on a per-function basis. The filename9384 for the dump is made by appending .su to the auxname. auxname is generated from the name of the output9385 file, if explicitly specified and it is not an executable, otherwise it is the basename of the source file.9386 An entry is made up of three fields:9387 * The name of the function.9388 * A number of bytes.9389 * One or more qualifiers: "static", "dynamic", "bounded".9390 The qualifier "static" means that the function manipulates the stack statically: a fixed number of bytes9391 are allocated for the frame on function entry and released on function exit; no stack adjustments are9392 otherwise made in the function. The second field is this fixed number of bytes.9393 The qualifier "dynamic" means that the function manipulates the stack dynamically: in addition to the9394 static allocation described above, stack adjustments are made in the body of the function, for example to9395 push/pop arguments around function calls. If the qualifier "bounded" is also present, the amount of these9396 adjustments is bounded at compile time and the second field is an upper bound of the total amount of stack9397 used by the function. If it is not present, the amount of these adjustments is not bounded at compile time9398 and the second field only represents the bounded part.9399 -fstats9400 Emit statistics about front-end processing at the end of the compilation. This option is supported only by9401 the C++ front end, and the information is generally only useful to the G++ development team.9402 -fdbg-cnt-list9403 Print the name and the counter upper bound for all debug counters.9404 -fdbg-cnt=counter-value-list9405 Set the internal debug counter lower and upper bound. counter-value-list is a comma-separated list of9406 name:lower_bound1-upper_bound1 [:lower_bound2-upper_bound2...] tuples which sets the name of the counter9407 and list of closed intervals. The lower_bound is optional and is zero initialized if not set. For9408 example, with -fdbg-cnt=dce:2-4:10-11,tail_call:10, "dbg_cnt(dce)" returns true only for second, third,9409 fourth, tenth and eleventh invocation. For "dbg_cnt(tail_call)" true is returned for first 10 invocations.9410 -print-file-name=library9411 Print the full absolute name of the library file library that would be used when linking---and don't do9412 anything else. With this option, GCC does not compile or link anything; it just prints the file name.9413 -print-multi-directory9414 Print the directory name corresponding to the multilib selected by any other switches present in the9415 command line. This directory is supposed to exist in GCC_EXEC_PREFIX.9416 -print-multi-lib9417 Print the mapping from multilib directory names to compiler switches that enable them. The directory name9418 is separated from the switches by ;, and each switch starts with an @ instead of the -, without spaces9419 between multiple switches. This is supposed to ease shell processing.9420 -print-multi-os-directory9421 Print the path to OS libraries for the selected multilib, relative to some lib subdirectory. If OS9422 libraries are present in the lib subdirectory and no multilibs are used, this is usually just ., if OS9423 libraries are present in libsuffix sibling directories this prints e.g. ../lib64, ../lib or ../lib32, or if9424 OS libraries are present in lib/subdir subdirectories it prints e.g. amd64, sparcv9 or ev6.9425 -print-multiarch9426 Print the path to OS libraries for the selected multiarch, relative to some lib subdirectory.9427 -print-prog-name=program9428 Like -print-file-name, but searches for a program such as cpp.9429 -print-libgcc-file-name9430 Same as -print-file-name=libgcc.a.9431 This is useful when you use -nostdlib or -nodefaultlibs but you do want to link with libgcc.a. You can do:9432 gcc -nostdlib ... `gcc -print-libgcc-file-name`9433 -print-search-dirs9434 Print the name of the configured installation directory and a list of program and library directories gcc9435 searches---and don't do anything else.9436 This is useful when gcc prints the error message installation problem, cannot exec cpp0: No such file or9437 directory. To resolve this you either need to put cpp0 and the other compiler components where gcc expects9438 to find them, or you can set the environment variable GCC_EXEC_PREFIX to the directory where you installed9439 them. Don't forget the trailing /.9440 -print-sysroot9441 Print the target sysroot directory that is used during compilation. This is the target sysroot specified9442 either at configure time or using the --sysroot option, possibly with an extra suffix that depends on9443 compilation options. If no target sysroot is specified, the option prints nothing.9444 -print-sysroot-headers-suffix9445 Print the suffix added to the target sysroot when searching for headers, or give an error if the compiler9446 is not configured with such a suffix---and don't do anything else.9447 -dumpmachine9448 Print the compiler's target machine (for example, i686-pc-linux-gnu)---and don't do anything else.9449 -dumpversion9450 Print the compiler version (for example, 3.0, 6.3.0 or 7)---and don't do anything else. This is the9451 compiler version used in filesystem paths and specs. Depending on how the compiler has been configured it9452 can be just a single number (major version), two numbers separated by a dot (major and minor version) or9453 three numbers separated by dots (major, minor and patchlevel version).9454 -dumpfullversion9455 Print the full compiler version---and don't do anything else. The output is always three numbers separated9456 by dots, major, minor and patchlevel version.9457 -dumpspecs9458 Print the compiler's built-in specs---and don't do anything else. (This is used when GCC itself is being9459 built.)9460 Machine-Dependent Options9461 Each target machine supported by GCC can have its own options---for example, to allow you to compile for a9462 particular processor variant or ABI, or to control optimizations specific to that machine. By convention, the9463 names of machine-specific options start with -m.9464 Some configurations of the compiler also support additional target-specific options, usually for compatibility9465 with other compilers on the same platform.9466 AArch64 Options9467 These options are defined for AArch64 implementations:9468 -mabi=name9469 Generate code for the specified data model. Permissible values are ilp32 for SysV-like data model where9470 int, long int and pointers are 32 bits, and lp64 for SysV-like data model where int is 32 bits, but long9471 int and pointers are 64 bits.9472 The default depends on the specific target configuration. Note that the LP64 and ILP32 ABIs are not link-9473 compatible; you must compile your entire program with the same ABI, and link with a compatible set of9474 libraries.9475 -mbig-endian9476 Generate big-endian code. This is the default when GCC is configured for an aarch64_be-*-* target.9477 -mgeneral-regs-only9478 Generate code which uses only the general-purpose registers. This will prevent the compiler from using9479 floating-point and Advanced SIMD registers but will not impose any restrictions on the assembler.9480 -mlittle-endian9481 Generate little-endian code. This is the default when GCC is configured for an aarch64-*-* but not an9482 aarch64_be-*-* target.9483 -mcmodel=tiny9484 Generate code for the tiny code model. The program and its statically defined symbols must be within 1MB9485 of each other. Programs can be statically or dynamically linked.9486 -mcmodel=small9487 Generate code for the small code model. The program and its statically defined symbols must be within 4GB9488 of each other. Programs can be statically or dynamically linked. This is the default code model.9489 -mcmodel=large9490 Generate code for the large code model. This makes no assumptions about addresses and sizes of sections.9491 Programs can be statically linked only. The -mcmodel=large option is incompatible with -mabi=ilp32, -fpic9492 and -fPIC.9493 -mstrict-align9494 -mno-strict-align9495 Avoid or allow generating memory accesses that may not be aligned on a natural object boundary as described9496 in the architecture specification.9497 -momit-leaf-frame-pointer9498 -mno-omit-leaf-frame-pointer9499 Omit or keep the frame pointer in leaf functions. The former behavior is the default.9500 -mstack-protector-guard=guard9501 -mstack-protector-guard-reg=reg9502 -mstack-protector-guard-offset=offset9503 Generate stack protection code using canary at guard. Supported locations are global for a global canary9504 or sysreg for a canary in an appropriate system register.9505 With the latter choice the options -mstack-protector-guard-reg=reg and9506 -mstack-protector-guard-offset=offset furthermore specify which system register to use as base register for9507 reading the canary, and from what offset from that base register. There is no default register or offset as9508 this is entirely for use within the Linux kernel.9509 -mtls-dialect=desc9510 Use TLS descriptors as the thread-local storage mechanism for dynamic accesses of TLS variables. This is9511 the default.9512 -mtls-dialect=traditional9513 Use traditional TLS as the thread-local storage mechanism for dynamic accesses of TLS variables.9514 -mtls-size=size9515 Specify bit size of immediate TLS offsets. Valid values are 12, 24, 32, 48. This option requires binutils9516 2.26 or newer.9517 -mfix-cortex-a53-8357699518 -mno-fix-cortex-a53-8357699519 Enable or disable the workaround for the ARM Cortex-A53 erratum number 835769. This involves inserting a9520 NOP instruction between memory instructions and 64-bit integer multiply-accumulate instructions.9521 -mfix-cortex-a53-8434199522 -mno-fix-cortex-a53-8434199523 Enable or disable the workaround for the ARM Cortex-A53 erratum number 843419. This erratum workaround is9524 made at link time and this will only pass the corresponding flag to the linker.9525 -mlow-precision-recip-sqrt9526 -mno-low-precision-recip-sqrt9527 Enable or disable the reciprocal square root approximation. This option only has an effect if -ffast-math9528 or -funsafe-math-optimizations is used as well. Enabling this reduces precision of reciprocal square root9529 results to about 16 bits for single precision and to 32 bits for double precision.9530 -mlow-precision-sqrt9531 -mno-low-precision-sqrt9532 Enable or disable the square root approximation. This option only has an effect if -ffast-math or9533 -funsafe-math-optimizations is used as well. Enabling this reduces precision of square root results to9534 about 16 bits for single precision and to 32 bits for double precision. If enabled, it implies9535 -mlow-precision-recip-sqrt.9536 -mlow-precision-div9537 -mno-low-precision-div9538 Enable or disable the division approximation. This option only has an effect if -ffast-math or9539 -funsafe-math-optimizations is used as well. Enabling this reduces precision of division results to about9540 16 bits for single precision and to 32 bits for double precision.9541 -mtrack-speculation9542 -mno-track-speculation9543 Enable or disable generation of additional code to track speculative execution through conditional9544 branches. The tracking state can then be used by the compiler when expanding calls to9545 "__builtin_speculation_safe_copy" to permit a more efficient code sequence to be generated.9546 -moutline-atomics9547 -mno-outline-atomics9548 Enable or disable calls to out-of-line helpers to implement atomic operations. These helpers will, at9549 runtime, determine if the LSE instructions from ARMv8.1-A can be used; if not, they will use the9550 load/store-exclusive instructions that are present in the base ARMv8.0 ISA.9551 This option is only applicable when compiling for the base ARMv8.0 instruction set. If using a later9552 revision, e.g. -march=armv8.1-a or -march=armv8-a+lse, the ARMv8.1-Atomics instructions will be used9553 directly. The same applies when using -mcpu= when the selected cpu supports the lse feature. This option9554 is on by default.9555 -march=name9556 Specify the name of the target architecture and, optionally, one or more feature modifiers. This option9557 has the form -march=arch{+[no]feature}*.9558 The table below summarizes the permissible values for arch and the features that they enable by default:9559 arch value : Architecture : Includes by default9560 armv8-a : Armv8-A : +fp, +simd9561 armv8.1-a : Armv8.1-A : armv8-a, +crc, +lse, +rdma9562 armv8.2-a : Armv8.2-A : armv8.1-a9563 armv8.3-a : Armv8.3-A : armv8.2-a, +pauth9564 armv8.4-a : Armv8.4-A : armv8.3-a, +flagm, +fp16fml, +dotprod9565 armv8.5-a : Armv8.5-A : armv8.4-a, +sb, +ssbs, +predres9566 armv8.6-a : Armv8.6-A : armv8.5-a, +bf16, +i8mm9567 armv8-r : Armv8-R : armv8-r9568 The value native is available on native AArch64 GNU/Linux and causes the compiler to pick the architecture9569 of the host system. This option has no effect if the compiler is unable to recognize the architecture of9570 the host system,9571 The permissible values for feature are listed in the sub-section on aarch64-feature-modifiers,,-march and9572 -mcpu Feature Modifiers. Where conflicting feature modifiers are specified, the right-most feature is9573 used.9574 GCC uses name to determine what kind of instructions it can emit when generating assembly code. If -march9575 is specified without either of -mtune or -mcpu also being specified, the code is tuned to perform well9576 across a range of target processors implementing the target architecture.9577 -mtune=name9578 Specify the name of the target processor for which GCC should tune the performance of the code.9579 Permissible values for this option are: generic, cortex-a35, cortex-a53, cortex-a55, cortex-a57,9580 cortex-a72, cortex-a73, cortex-a75, cortex-a76, cortex-a76ae, cortex-a77, cortex-a65, cortex-a65ae,9581 cortex-a34, cortex-a78, cortex-a78ae, cortex-a78c, ares, exynos-m1, emag, falkor, neoverse-512tvb,9582 neoverse-e1, neoverse-n1, neoverse-n2, neoverse-v1, qdf24xx, saphira, phecda, xgene1, vulcan, octeontx,9583 octeontx81, octeontx83, octeontx2, octeontx2t98, octeontx2t96 octeontx2t93, octeontx2f95, octeontx2f95n,9584 octeontx2f95mm, a64fx, thunderx, thunderxt88, thunderxt88p1, thunderxt81, tsv110, thunderxt83,9585 thunderx2t99, thunderx3t110, zeus, cortex-a57.cortex-a53, cortex-a72.cortex-a53, cortex-a73.cortex-a35,9586 cortex-a73.cortex-a53, cortex-a75.cortex-a55, cortex-a76.cortex-a55, cortex-r82, cortex-x1, ampere1,9587 native.9588 The values cortex-a57.cortex-a53, cortex-a72.cortex-a53, cortex-a73.cortex-a35, cortex-a73.cortex-a53,9589 cortex-a75.cortex-a55, cortex-a76.cortex-a55 specify that GCC should tune for a big.LITTLE system.9590 The value neoverse-512tvb specifies that GCC should tune for Neoverse cores that (a) implement SVE and (b)9591 have a total vector bandwidth of 512 bits per cycle. In other words, the option tells GCC to tune for9592 Neoverse cores that can execute 4 128-bit Advanced SIMD arithmetic instructions a cycle and that can9593 execute an equivalent number of SVE arithmetic instructions per cycle (2 for 256-bit SVE, 4 for 128-bit9594 SVE). This is more general than tuning for a specific core like Neoverse V1 but is more specific than the9595 default tuning described below.9596 Additionally on native AArch64 GNU/Linux systems the value native tunes performance to the host system.9597 This option has no effect if the compiler is unable to recognize the processor of the host system.9598 Where none of -mtune=, -mcpu= or -march= are specified, the code is tuned to perform well across a range of9599 target processors.9600 This option cannot be suffixed by feature modifiers.9601 -mcpu=name9602 Specify the name of the target processor, optionally suffixed by one or more feature modifiers. This9603 option has the form -mcpu=cpu{+[no]feature}*, where the permissible values for cpu are the same as those9604 available for -mtune. The permissible values for feature are documented in the sub-section on9605 aarch64-feature-modifiers,,-march and -mcpu Feature Modifiers. Where conflicting feature modifiers are9606 specified, the right-most feature is used.9607 GCC uses name to determine what kind of instructions it can emit when generating assembly code (as if by9608 -march) and to determine the target processor for which to tune for performance (as if by -mtune). Where9609 this option is used in conjunction with -march or -mtune, those options take precedence over the9610 appropriate part of this option.9611 -mcpu=neoverse-512tvb is special in that it does not refer to a specific core, but instead refers to all9612 Neoverse cores that (a) implement SVE and (b) have a total vector bandwidth of 512 bits a cycle. Unless9613 overridden by -march, -mcpu=neoverse-512tvb generates code that can run on a Neoverse V1 core, since9614 Neoverse V1 is the first Neoverse core with these properties. Unless overridden by -mtune,9615 -mcpu=neoverse-512tvb tunes code in the same way as for -mtune=neoverse-512tvb.9616 -moverride=string9617 Override tuning decisions made by the back-end in response to a -mtune= switch. The syntax, semantics, and9618 accepted values for string in this option are not guaranteed to be consistent across releases.9619 This option is only intended to be useful when developing GCC.9620 -mverbose-cost-dump9621 Enable verbose cost model dumping in the debug dump files. This option is provided for use in debugging9622 the compiler.9623 -mpc-relative-literal-loads9624 -mno-pc-relative-literal-loads9625 Enable or disable PC-relative literal loads. With this option literal pools are accessed using a single9626 instruction and emitted after each function. This limits the maximum size of functions to 1MB. This is9627 enabled by default for -mcmodel=tiny.9628 -msign-return-address=scope9629 Select the function scope on which return address signing will be applied. Permissible values are none,9630 which disables return address signing, non-leaf, which enables pointer signing for functions which are not9631 leaf functions, and all, which enables pointer signing for all functions. The default value is none. This9632 option has been deprecated by -mbranch-protection.9633 -mbranch-protection=none|standard|pac-ret[+leaf+b-key]|bti9634 Select the branch protection features to use. none is the default and turns off all types of branch9635 protection. standard turns on all types of branch protection features. If a feature has additional tuning9636 options, then standard sets it to its standard level. pac-ret[+leaf] turns on return address signing to9637 its standard level: signing functions that save the return address to memory (non-leaf functions will9638 practically always do this) using the a-key. The optional argument leaf can be used to extend the signing9639 to include leaf functions. The optional argument b-key can be used to sign the functions with the B-key9640 instead of the A-key. bti turns on branch target identification mechanism.9641 -mharden-sls=opts9642 Enable compiler hardening against straight line speculation (SLS). opts is a comma-separated list of the9643 following options:9644 retbr9645 blr9646 In addition, -mharden-sls=all enables all SLS hardening while -mharden-sls=none disables all SLS hardening.9647 -msve-vector-bits=bits9648 Specify the number of bits in an SVE vector register. This option only has an effect when SVE is enabled.9649 GCC supports two forms of SVE code generation: "vector-length agnostic" output that works with any size of9650 vector register and "vector-length specific" output that allows GCC to make assumptions about the vector9651 length when it is useful for optimization reasons. The possible values of bits are: scalable, 128, 256,9652 512, 1024 and 2048. Specifying scalable selects vector-length agnostic output. At present9653 -msve-vector-bits=128 also generates vector-length agnostic output for big-endian targets. All other9654 values generate vector-length specific code. The behavior of these values may change in future releases9655 and no value except scalable should be relied on for producing code that is portable across different9656 hardware SVE vector lengths.9657 The default is -msve-vector-bits=scalable, which produces vector-length agnostic code.9658 -march and -mcpu Feature Modifiers9659 Feature modifiers used with -march and -mcpu can be any of the following and their inverses nofeature:9660 crc Enable CRC extension. This is on by default for -march=armv8.1-a.9661 crypto9662 Enable Crypto extension. This also enables Advanced SIMD and floating-point instructions.9663 fp Enable floating-point instructions. This is on by default for all possible values for options -march and9664 -mcpu.9665 simd9666 Enable Advanced SIMD instructions. This also enables floating-point instructions. This is on by default9667 for all possible values for options -march and -mcpu.9668 sve Enable Scalable Vector Extension instructions. This also enables Advanced SIMD and floating-point9669 instructions.9670 lse Enable Large System Extension instructions. This is on by default for -march=armv8.1-a.9671 rdma9672 Enable Round Double Multiply Accumulate instructions. This is on by default for -march=armv8.1-a.9673 fp169674 Enable FP16 extension. This also enables floating-point instructions.9675 fp16fml9676 Enable FP16 fmla extension. This also enables FP16 extensions and floating-point instructions. This option9677 is enabled by default for -march=armv8.4-a. Use of this option with architectures prior to Armv8.2-A is not9678 supported.9679 rcpc9680 Enable the RcPc extension. This does not change code generation from GCC, but is passed on to the9681 assembler, enabling inline asm statements to use instructions from the RcPc extension.9682 dotprod9683 Enable the Dot Product extension. This also enables Advanced SIMD instructions.9684 aes Enable the Armv8-a aes and pmull crypto extension. This also enables Advanced SIMD instructions.9685 sha29686 Enable the Armv8-a sha2 crypto extension. This also enables Advanced SIMD instructions.9687 sha39688 Enable the sha512 and sha3 crypto extension. This also enables Advanced SIMD instructions. Use of this9689 option with architectures prior to Armv8.2-A is not supported.9690 sm4 Enable the sm3 and sm4 crypto extension. This also enables Advanced SIMD instructions. Use of this option9691 with architectures prior to Armv8.2-A is not supported.9692 profile9693 Enable the Statistical Profiling extension. This option is only to enable the extension at the assembler9694 level and does not affect code generation.9695 rng Enable the Armv8.5-a Random Number instructions. This option is only to enable the extension at the9696 assembler level and does not affect code generation.9697 memtag9698 Enable the Armv8.5-a Memory Tagging Extensions. Use of this option with architectures prior to Armv8.5-A9699 is not supported.9700 sb Enable the Armv8-a Speculation Barrier instruction. This option is only to enable the extension at the9701 assembler level and does not affect code generation. This option is enabled by default for9702 -march=armv8.5-a.9703 ssbs9704 Enable the Armv8-a Speculative Store Bypass Safe instruction. This option is only to enable the extension9705 at the assembler level and does not affect code generation. This option is enabled by default for9706 -march=armv8.5-a.9707 predres9708 Enable the Armv8-a Execution and Data Prediction Restriction instructions. This option is only to enable9709 the extension at the assembler level and does not affect code generation. This option is enabled by9710 default for -march=armv8.5-a.9711 sve29712 Enable the Armv8-a Scalable Vector Extension 2. This also enables SVE instructions.9713 sve2-bitperm9714 Enable SVE2 bitperm instructions. This also enables SVE2 instructions.9715 sve2-sm49716 Enable SVE2 sm4 instructions. This also enables SVE2 instructions.9717 sve2-aes9718 Enable SVE2 aes instructions. This also enables SVE2 instructions.9719 sve2-sha39720 Enable SVE2 sha3 instructions. This also enables SVE2 instructions.9721 tme Enable the Transactional Memory Extension.9722 i8mm9723 Enable 8-bit Integer Matrix Multiply instructions. This also enables Advanced SIMD and floating-point9724 instructions. This option is enabled by default for -march=armv8.6-a. Use of this option with9725 architectures prior to Armv8.2-A is not supported.9726 f32mm9727 Enable 32-bit Floating point Matrix Multiply instructions. This also enables SVE instructions. Use of9728 this option with architectures prior to Armv8.2-A is not supported.9729 f64mm9730 Enable 64-bit Floating point Matrix Multiply instructions. This also enables SVE instructions. Use of9731 this option with architectures prior to Armv8.2-A is not supported.9732 bf169733 Enable brain half-precision floating-point instructions. This also enables Advanced SIMD and floating-9734 point instructions. This option is enabled by default for -march=armv8.6-a. Use of this option with9735 architectures prior to Armv8.2-A is not supported.9736 flagm9737 Enable the Flag Manipulation instructions Extension.9738 pauth9739 Enable the Pointer Authentication Extension.9740 Feature crypto implies aes, sha2, and simd, which implies fp. Conversely, nofp implies nosimd, which implies9741 nocrypto, noaes and nosha2.9742 Adapteva Epiphany Options9743 These -m options are defined for Adapteva Epiphany:9744 -mhalf-reg-file9745 Don't allocate any register in the range "r32"..."r63". That allows code to run on hardware variants that9746 lack these registers.9747 -mprefer-short-insn-regs9748 Preferentially allocate registers that allow short instruction generation. This can result in increased9749 instruction count, so this may either reduce or increase overall code size.9750 -mbranch-cost=num9751 Set the cost of branches to roughly num "simple" instructions. This cost is only a heuristic and is not9752 guaranteed to produce consistent results across releases.9753 -mcmove9754 Enable the generation of conditional moves.9755 -mnops=num9756 Emit num NOPs before every other generated instruction.9757 -mno-soft-cmpsf9758 For single-precision floating-point comparisons, emit an "fsub" instruction and test the flags. This is9759 faster than a software comparison, but can get incorrect results in the presence of NaNs, or when two9760 different small numbers are compared such that their difference is calculated as zero. The default is9761 -msoft-cmpsf, which uses slower, but IEEE-compliant, software comparisons.9762 -mstack-offset=num9763 Set the offset between the top of the stack and the stack pointer. E.g., a value of 8 means that the eight9764 bytes in the range "sp+0...sp+7" can be used by leaf functions without stack allocation. Values other than9765 8 or 16 are untested and unlikely to work. Note also that this option changes the ABI; compiling a program9766 with a different stack offset than the libraries have been compiled with generally does not work. This9767 option can be useful if you want to evaluate if a different stack offset would give you better code, but to9768 actually use a different stack offset to build working programs, it is recommended to configure the9769 toolchain with the appropriate --with-stack-offset=num option.9770 -mno-round-nearest9771 Make the scheduler assume that the rounding mode has been set to truncating. The default is9772 -mround-nearest.9773 -mlong-calls9774 If not otherwise specified by an attribute, assume all calls might be beyond the offset range of the "b" /9775 "bl" instructions, and therefore load the function address into a register before performing a (otherwise9776 direct) call. This is the default.9777 -mshort-calls9778 If not otherwise specified by an attribute, assume all direct calls are in the range of the "b" / "bl"9779 instructions, so use these instructions for direct calls. The default is -mlong-calls.9780 -msmall169781 Assume addresses can be loaded as 16-bit unsigned values. This does not apply to function addresses for9782 which -mlong-calls semantics are in effect.9783 -mfp-mode=mode9784 Set the prevailing mode of the floating-point unit. This determines the floating-point mode that is9785 provided and expected at function call and return time. Making this mode match the mode you predominantly9786 need at function start can make your programs smaller and faster by avoiding unnecessary mode switches.9787 mode can be set to one the following values:9788 caller9789 Any mode at function entry is valid, and retained or restored when the function returns, and when it9790 calls other functions. This mode is useful for compiling libraries or other compilation units you9791 might want to incorporate into different programs with different prevailing FPU modes, and the9792 convenience of being able to use a single object file outweighs the size and speed overhead for any9793 extra mode switching that might be needed, compared with what would be needed with a more specific9794 choice of prevailing FPU mode.9795 truncate9796 This is the mode used for floating-point calculations with truncating (i.e. round towards zero)9797 rounding mode. That includes conversion from floating point to integer.9798 round-nearest9799 This is the mode used for floating-point calculations with round-to-nearest-or-even rounding mode.9800 int This is the mode used to perform integer calculations in the FPU, e.g. integer multiply, or integer9801 multiply-and-accumulate.9802 The default is -mfp-mode=caller9803 -mno-split-lohi9804 -mno-postinc9805 -mno-postmodify9806 Code generation tweaks that disable, respectively, splitting of 32-bit loads, generation of post-increment9807 addresses, and generation of post-modify addresses. The defaults are msplit-lohi, -mpost-inc, and9808 -mpost-modify.9809 -mnovect-double9810 Change the preferred SIMD mode to SImode. The default is -mvect-double, which uses DImode as preferred9811 SIMD mode.9812 -max-vect-align=num9813 The maximum alignment for SIMD vector mode types. num may be 4 or 8. The default is 8. Note that this is9814 an ABI change, even though many library function interfaces are unaffected if they don't use SIMD vector9815 modes in places that affect size and/or alignment of relevant types.9816 -msplit-vecmove-early9817 Split vector moves into single word moves before reload. In theory this can give better register9818 allocation, but so far the reverse seems to be generally the case.9819 -m1reg-reg9820 Specify a register to hold the constant -1, which makes loading small negative constants and certain9821 bitmasks faster. Allowable values for reg are r43 and r63, which specify use of that register as a fixed9822 register, and none, which means that no register is used for this purpose. The default is -m1reg-none.9823 AMD GCN Options9824 These options are defined specifically for the AMD GCN port.9825 -march=gpu9826 -mtune=gpu9827 Set architecture type or tuning for gpu. Supported values for gpu are9828 fiji9829 Compile for GCN3 Fiji devices (gfx803).9830 gfx9009831 Compile for GCN5 Vega 10 devices (gfx900).9832 gfx9069833 Compile for GCN5 Vega 20 devices (gfx906).9834 -msram-ecc=on9835 -msram-ecc=off9836 -msram-ecc=any9837 Compile binaries suitable for devices with the SRAM-ECC feature enabled, disabled, or either mode. This9838 feature can be enabled per-process on some devices. The compiled code must match the device mode. The9839 default is any, for devices that support it.9840 -mstack-size=bytes9841 Specify how many bytes of stack space will be requested for each GPU thread (wave-front). Beware that9842 there may be many threads and limited memory available. The size of the stack allocation may also have an9843 impact on run-time performance. The default is 32KB when using OpenACC or OpenMP, and 1MB otherwise.9844 -mxnack9845 Compile binaries suitable for devices with the XNACK feature enabled. Some devices always require XNACK9846 and some allow the user to configure XNACK. The compiled code must match the device mode. The default is9847 -mno-xnack. At present this option is a placeholder for support that is not yet implemented.9848 ARC Options9849 The following options control the architecture variant for which code is being compiled:9850 -mbarrel-shifter9851 Generate instructions supported by barrel shifter. This is the default unless -mcpu=ARC601 or -mcpu=ARCEM9852 is in effect.9853 -mjli-always9854 Force to call a function using jli_s instruction. This option is valid only for ARCv2 architecture.9855 -mcpu=cpu9856 Set architecture type, register usage, and instruction scheduling parameters for cpu. There are also9857 shortcut alias options available for backward compatibility and convenience. Supported values for cpu are9858 arc6009859 Compile for ARC600. Aliases: -mA6, -mARC600.9860 arc6019861 Compile for ARC601. Alias: -mARC601.9862 arc7009863 Compile for ARC700. Aliases: -mA7, -mARC700. This is the default when configured with9864 --with-cpu=arc700.9865 arcem9866 Compile for ARC EM.9867 archs9868 Compile for ARC HS.9869 em Compile for ARC EM CPU with no hardware extensions.9870 em4 Compile for ARC EM4 CPU.9871 em4_dmips9872 Compile for ARC EM4 DMIPS CPU.9873 em4_fpus9874 Compile for ARC EM4 DMIPS CPU with the single-precision floating-point extension.9875 em4_fpuda9876 Compile for ARC EM4 DMIPS CPU with single-precision floating-point and double assist instructions.9877 hs Compile for ARC HS CPU with no hardware extensions except the atomic instructions.9878 hs349879 Compile for ARC HS34 CPU.9880 hs389881 Compile for ARC HS38 CPU.9882 hs38_linux9883 Compile for ARC HS38 CPU with all hardware extensions on.9884 arc600_norm9885 Compile for ARC 600 CPU with "norm" instructions enabled.9886 arc600_mul32x169887 Compile for ARC 600 CPU with "norm" and 32x16-bit multiply instructions enabled.9888 arc600_mul649889 Compile for ARC 600 CPU with "norm" and "mul64"-family instructions enabled.9890 arc601_norm9891 Compile for ARC 601 CPU with "norm" instructions enabled.9892 arc601_mul32x169893 Compile for ARC 601 CPU with "norm" and 32x16-bit multiply instructions enabled.9894 arc601_mul649895 Compile for ARC 601 CPU with "norm" and "mul64"-family instructions enabled.9896 nps4009897 Compile for ARC 700 on NPS400 chip.9898 em_mini9899 Compile for ARC EM minimalist configuration featuring reduced register set.9900 -mdpfp9901 -mdpfp-compact9902 Generate double-precision FPX instructions, tuned for the compact implementation.9903 -mdpfp-fast9904 Generate double-precision FPX instructions, tuned for the fast implementation.9905 -mno-dpfp-lrsr9906 Disable "lr" and "sr" instructions from using FPX extension aux registers.9907 -mea9908 Generate extended arithmetic instructions. Currently only "divaw", "adds", "subs", and "sat16" are9909 supported. Only valid for -mcpu=ARC700.9910 -mno-mpy9911 Do not generate "mpy"-family instructions for ARC700. This option is deprecated.9912 -mmul32x169913 Generate 32x16-bit multiply and multiply-accumulate instructions.9914 -mmul649915 Generate "mul64" and "mulu64" instructions. Only valid for -mcpu=ARC600.9916 -mnorm9917 Generate "norm" instructions. This is the default if -mcpu=ARC700 is in effect.9918 -mspfp9919 -mspfp-compact9920 Generate single-precision FPX instructions, tuned for the compact implementation.9921 -mspfp-fast9922 Generate single-precision FPX instructions, tuned for the fast implementation.9923 -msimd9924 Enable generation of ARC SIMD instructions via target-specific builtins. Only valid for -mcpu=ARC700.9925 -msoft-float9926 This option ignored; it is provided for compatibility purposes only. Software floating-point code is9927 emitted by default, and this default can overridden by FPX options; -mspfp, -mspfp-compact, or -mspfp-fast9928 for single precision, and -mdpfp, -mdpfp-compact, or -mdpfp-fast for double precision.9929 -mswap9930 Generate "swap" instructions.9931 -matomic9932 This enables use of the locked load/store conditional extension to implement atomic memory built-in9933 functions. Not available for ARC 6xx or ARC EM cores.9934 -mdiv-rem9935 Enable "div" and "rem" instructions for ARCv2 cores.9936 -mcode-density9937 Enable code density instructions for ARC EM. This option is on by default for ARC HS.9938 -mll649939 Enable double load/store operations for ARC HS cores.9940 -mtp-regno=regno9941 Specify thread pointer register number.9942 -mmpy-option=multo9943 Compile ARCv2 code with a multiplier design option. You can specify the option using either a string or9944 numeric value for multo. wlh1 is the default value. The recognized values are:9945 09946 none9947 No multiplier available.9948 19949 w 16x16 multiplier, fully pipelined. The following instructions are enabled: "mpyw" and "mpyuw".9950 29951 wlh19952 32x32 multiplier, fully pipelined (1 stage). The following instructions are additionally enabled:9953 "mpy", "mpyu", "mpym", "mpymu", and "mpy_s".9954 39955 wlh29956 32x32 multiplier, fully pipelined (2 stages). The following instructions are additionally enabled:9957 "mpy", "mpyu", "mpym", "mpymu", and "mpy_s".9958 49959 wlh39960 Two 16x16 multipliers, blocking, sequential. The following instructions are additionally enabled:9961 "mpy", "mpyu", "mpym", "mpymu", and "mpy_s".9962 59963 wlh49964 One 16x16 multiplier, blocking, sequential. The following instructions are additionally enabled:9965 "mpy", "mpyu", "mpym", "mpymu", and "mpy_s".9966 69967 wlh59968 One 32x4 multiplier, blocking, sequential. The following instructions are additionally enabled: "mpy",9969 "mpyu", "mpym", "mpymu", and "mpy_s".9970 79971 plus_dmpy9972 ARC HS SIMD support.9973 89974 plus_macd9975 ARC HS SIMD support.9976 99977 plus_qmacw9978 ARC HS SIMD support.9979 This option is only available for ARCv2 cores.9980 -mfpu=fpu9981 Enables support for specific floating-point hardware extensions for ARCv2 cores. Supported values for fpu9982 are:9983 fpus9984 Enables support for single-precision floating-point hardware extensions.9985 fpud9986 Enables support for double-precision floating-point hardware extensions. The single-precision9987 floating-point extension is also enabled. Not available for ARC EM.9988 fpuda9989 Enables support for double-precision floating-point hardware extensions using double-precision assist9990 instructions. The single-precision floating-point extension is also enabled. This option is only9991 available for ARC EM.9992 fpuda_div9993 Enables support for double-precision floating-point hardware extensions using double-precision assist9994 instructions. The single-precision floating-point, square-root, and divide extensions are also9995 enabled. This option is only available for ARC EM.9996 fpuda_fma9997 Enables support for double-precision floating-point hardware extensions using double-precision assist9998 instructions. The single-precision floating-point and fused multiply and add hardware extensions are9999 also enabled. This option is only available for ARC EM.10000 fpuda_all10001 Enables support for double-precision floating-point hardware extensions using double-precision assist10002 instructions. All single-precision floating-point hardware extensions are also enabled. This option10003 is only available for ARC EM.10004 fpus_div10005 Enables support for single-precision floating-point, square-root and divide hardware extensions.10006 fpud_div10007 Enables support for double-precision floating-point, square-root and divide hardware extensions. This10008 option includes option fpus_div. Not available for ARC EM.10009 fpus_fma10010 Enables support for single-precision floating-point and fused multiply and add hardware extensions.10011 fpud_fma10012 Enables support for double-precision floating-point and fused multiply and add hardware extensions.10013 This option includes option fpus_fma. Not available for ARC EM.10014 fpus_all10015 Enables support for all single-precision floating-point hardware extensions.10016 fpud_all10017 Enables support for all single- and double-precision floating-point hardware extensions. Not available10018 for ARC EM.10019 -mirq-ctrl-saved=register-range, blink, lp_count10020 Specifies general-purposes registers that the processor automatically saves/restores on interrupt entry and10021 exit. register-range is specified as two registers separated by a dash. The register range always starts10022 with "r0", the upper limit is "fp" register. blink and lp_count are optional. This option is only valid10023 for ARC EM and ARC HS cores.10024 -mrgf-banked-regs=number10025 Specifies the number of registers replicated in second register bank on entry to fast interrupt. Fast10026 interrupts are interrupts with the highest priority level P0. These interrupts save only PC and STATUS3210027 registers to avoid memory transactions during interrupt entry and exit sequences. Use this option when you10028 are using fast interrupts in an ARC V2 family processor. Permitted values are 4, 8, 16, and 32.10029 -mlpc-width=width10030 Specify the width of the "lp_count" register. Valid values for width are 8, 16, 20, 24, 28 and 32 bits.10031 The default width is fixed to 32 bits. If the width is less than 32, the compiler does not attempt to10032 transform loops in your program to use the zero-delay loop mechanism unless it is known that the "lp_count"10033 register can hold the required loop-counter value. Depending on the width specified, the compiler and run-10034 time library might continue to use the loop mechanism for various needs. This option defines macro10035 "__ARC_LPC_WIDTH__" with the value of width.10036 -mrf1610037 This option instructs the compiler to generate code for a 16-entry register file. This option defines the10038 "__ARC_RF16__" preprocessor macro.10039 -mbranch-index10040 Enable use of "bi" or "bih" instructions to implement jump tables.10041 The following options are passed through to the assembler, and also define preprocessor macro symbols.10042 -mdsp-packa10043 Passed down to the assembler to enable the DSP Pack A extensions. Also sets the preprocessor symbol10044 "__Xdsp_packa". This option is deprecated.10045 -mdvbf10046 Passed down to the assembler to enable the dual Viterbi butterfly extension. Also sets the preprocessor10047 symbol "__Xdvbf". This option is deprecated.10048 -mlock10049 Passed down to the assembler to enable the locked load/store conditional extension. Also sets the10050 preprocessor symbol "__Xlock".10051 -mmac-d1610052 Passed down to the assembler. Also sets the preprocessor symbol "__Xxmac_d16". This option is deprecated.10053 -mmac-2410054 Passed down to the assembler. Also sets the preprocessor symbol "__Xxmac_24". This option is deprecated.10055 -mrtsc10056 Passed down to the assembler to enable the 64-bit time-stamp counter extension instruction. Also sets the10057 preprocessor symbol "__Xrtsc". This option is deprecated.10058 -mswape10059 Passed down to the assembler to enable the swap byte ordering extension instruction. Also sets the10060 preprocessor symbol "__Xswape".10061 -mtelephony10062 Passed down to the assembler to enable dual- and single-operand instructions for telephony. Also sets the10063 preprocessor symbol "__Xtelephony". This option is deprecated.10064 -mxy10065 Passed down to the assembler to enable the XY memory extension. Also sets the preprocessor symbol "__Xxy".10066 The following options control how the assembly code is annotated:10067 -misize10068 Annotate assembler instructions with estimated addresses.10069 -mannotate-align10070 Explain what alignment considerations lead to the decision to make an instruction short or long.10071 The following options are passed through to the linker:10072 -marclinux10073 Passed through to the linker, to specify use of the "arclinux" emulation. This option is enabled by10074 default in tool chains built for "arc-linux-uclibc" and "arceb-linux-uclibc" targets when profiling is not10075 requested.10076 -marclinux_prof10077 Passed through to the linker, to specify use of the "arclinux_prof" emulation. This option is enabled by10078 default in tool chains built for "arc-linux-uclibc" and "arceb-linux-uclibc" targets when profiling is10079 requested.10080 The following options control the semantics of generated code:10081 -mlong-calls10082 Generate calls as register indirect calls, thus providing access to the full 32-bit address range.10083 -mmedium-calls10084 Don't use less than 25-bit addressing range for calls, which is the offset available for an unconditional10085 branch-and-link instruction. Conditional execution of function calls is suppressed, to allow use of the10086 25-bit range, rather than the 21-bit range with conditional branch-and-link. This is the default for tool10087 chains built for "arc-linux-uclibc" and "arceb-linux-uclibc" targets.10088 -G num10089 Put definitions of externally-visible data in a small data section if that data is no bigger than num10090 bytes. The default value of num is 4 for any ARC configuration, or 8 when we have double load/store10091 operations.10092 -mno-sdata10093 Do not generate sdata references. This is the default for tool chains built for "arc-linux-uclibc" and10094 "arceb-linux-uclibc" targets.10095 -mvolatile-cache10096 Use ordinarily cached memory accesses for volatile references. This is the default.10097 -mno-volatile-cache10098 Enable cache bypass for volatile references.10099 The following options fine tune code generation:10100 -malign-call10101 Do alignment optimizations for call instructions.10102 -mauto-modify-reg10103 Enable the use of pre/post modify with register displacement.10104 -mbbit-peephole10105 Enable bbit peephole2.10106 -mno-brcc10107 This option disables a target-specific pass in arc_reorg to generate compare-and-branch ("brcc")10108 instructions. It has no effect on generation of these instructions driven by the combiner pass.10109 -mcase-vector-pcrel10110 Use PC-relative switch case tables to enable case table shortening. This is the default for -Os.10111 -mcompact-casesi10112 Enable compact "casesi" pattern. This is the default for -Os, and only available for ARCv1 cores. This10113 option is deprecated.10114 -mno-cond-exec10115 Disable the ARCompact-specific pass to generate conditional execution instructions.10116 Due to delay slot scheduling and interactions between operand numbers, literal sizes, instruction lengths,10117 and the support for conditional execution, the target-independent pass to generate conditional execution is10118 often lacking, so the ARC port has kept a special pass around that tries to find more conditional execution10119 generation opportunities after register allocation, branch shortening, and delay slot scheduling have been10120 done. This pass generally, but not always, improves performance and code size, at the cost of extra10121 compilation time, which is why there is an option to switch it off. If you have a problem with call10122 instructions exceeding their allowable offset range because they are conditionalized, you should consider10123 using -mmedium-calls instead.10124 -mearly-cbranchsi10125 Enable pre-reload use of the "cbranchsi" pattern.10126 -mexpand-adddi10127 Expand "adddi3" and "subdi3" at RTL generation time into "add.f", "adc" etc. This option is deprecated.10128 -mindexed-loads10129 Enable the use of indexed loads. This can be problematic because some optimizers then assume that indexed10130 stores exist, which is not the case.10131 -mlra10132 Enable Local Register Allocation. This is still experimental for ARC, so by default the compiler uses10133 standard reload (i.e. -mno-lra).10134 -mlra-priority-none10135 Don't indicate any priority for target registers.10136 -mlra-priority-compact10137 Indicate target register priority for r0..r3 / r12..r15.10138 -mlra-priority-noncompact10139 Reduce target register priority for r0..r3 / r12..r15.10140 -mmillicode10141 When optimizing for size (using -Os), prologues and epilogues that have to save or restore a large number10142 of registers are often shortened by using call to a special function in libgcc; this is referred to as a10143 millicode call. As these calls can pose performance issues, and/or cause linking issues when linking in a10144 nonstandard way, this option is provided to turn on or off millicode call generation.10145 -mcode-density-frame10146 This option enable the compiler to emit "enter" and "leave" instructions. These instructions are only10147 valid for CPUs with code-density feature.10148 -mmixed-code10149 Tweak register allocation to help 16-bit instruction generation. This generally has the effect of10150 decreasing the average instruction size while increasing the instruction count.10151 -mq-class10152 Ths option is deprecated. Enable q instruction alternatives. This is the default for -Os.10153 -mRcq10154 Enable Rcq constraint handling. Most short code generation depends on this. This is the default.10155 -mRcw10156 Enable Rcw constraint handling. Most ccfsm condexec mostly depends on this. This is the default.10157 -msize-level=level10158 Fine-tune size optimization with regards to instruction lengths and alignment. The recognized values for10159 level are:10160 0 No size optimization. This level is deprecated and treated like 1.10161 1 Short instructions are used opportunistically.10162 2 In addition, alignment of loops and of code after barriers are dropped.10163 3 In addition, optional data alignment is dropped, and the option Os is enabled.10164 This defaults to 3 when -Os is in effect. Otherwise, the behavior when this is not set is equivalent to10165 level 1.10166 -mtune=cpu10167 Set instruction scheduling parameters for cpu, overriding any implied by -mcpu=.10168 Supported values for cpu are10169 ARC60010170 Tune for ARC600 CPU.10171 ARC60110172 Tune for ARC601 CPU.10173 ARC70010174 Tune for ARC700 CPU with standard multiplier block.10175 ARC700-xmac10176 Tune for ARC700 CPU with XMAC block.10177 ARC725D10178 Tune for ARC725D CPU.10179 ARC750D10180 Tune for ARC750D CPU.10181 -mmultcost=num10182 Cost to assume for a multiply instruction, with 4 being equal to a normal instruction.10183 -munalign-prob-threshold=probability10184 Set probability threshold for unaligning branches. When tuning for ARC700 and optimizing for speed,10185 branches without filled delay slot are preferably emitted unaligned and long, unless profiling indicates10186 that the probability for the branch to be taken is below probability. The default is (REG_BR_PROB_BASE/2),10187 i.e. 5000.10188 The following options are maintained for backward compatibility, but are now deprecated and will be removed in10189 a future release:10190 -margonaut10191 Obsolete FPX.10192 -mbig-endian10193 -EB Compile code for big-endian targets. Use of these options is now deprecated. Big-endian code is supported10194 by configuring GCC to build "arceb-elf32" and "arceb-linux-uclibc" targets, for which big endian is the10195 default.10196 -mlittle-endian10197 -EL Compile code for little-endian targets. Use of these options is now deprecated. Little-endian code is10198 supported by configuring GCC to build "arc-elf32" and "arc-linux-uclibc" targets, for which little endian10199 is the default.10200 -mbarrel_shifter10201 Replaced by -mbarrel-shifter.10202 -mdpfp_compact10203 Replaced by -mdpfp-compact.10204 -mdpfp_fast10205 Replaced by -mdpfp-fast.10206 -mdsp_packa10207 Replaced by -mdsp-packa.10208 -mEA10209 Replaced by -mea.10210 -mmac_2410211 Replaced by -mmac-24.10212 -mmac_d1610213 Replaced by -mmac-d16.10214 -mspfp_compact10215 Replaced by -mspfp-compact.10216 -mspfp_fast10217 Replaced by -mspfp-fast.10218 -mtune=cpu10219 Values arc600, arc601, arc700 and arc700-xmac for cpu are replaced by ARC600, ARC601, ARC700 and10220 ARC700-xmac respectively.10221 -multcost=num10222 Replaced by -mmultcost.10223 ARM Options10224 These -m options are defined for the ARM port:10225 -mabi=name10226 Generate code for the specified ABI. Permissible values are: apcs-gnu, atpcs, aapcs, aapcs-linux and10227 iwmmxt.10228 -mapcs-frame10229 Generate a stack frame that is compliant with the ARM Procedure Call Standard for all functions, even if10230 this is not strictly necessary for correct execution of the code. Specifying -fomit-frame-pointer with10231 this option causes the stack frames not to be generated for leaf functions. The default is10232 -mno-apcs-frame. This option is deprecated.10233 -mapcs10234 This is a synonym for -mapcs-frame and is deprecated.10235 -mthumb-interwork10236 Generate code that supports calling between the ARM and Thumb instruction sets. Without this option, on10237 pre-v5 architectures, the two instruction sets cannot be reliably used inside one program. The default is10238 -mno-thumb-interwork, since slightly larger code is generated when -mthumb-interwork is specified. In10239 AAPCS configurations this option is meaningless.10240 -mno-sched-prolog10241 Prevent the reordering of instructions in the function prologue, or the merging of those instruction with10242 the instructions in the function's body. This means that all functions start with a recognizable set of10243 instructions (or in fact one of a choice from a small set of different function prologues), and this10244 information can be used to locate the start of functions inside an executable piece of code. The default10245 is -msched-prolog.10246 -mfloat-abi=name10247 Specifies which floating-point ABI to use. Permissible values are: soft, softfp and hard.10248 Specifying soft causes GCC to generate output containing library calls for floating-point operations.10249 softfp allows the generation of code using hardware floating-point instructions, but still uses the soft-10250 float calling conventions. hard allows generation of floating-point instructions and uses FPU-specific10251 calling conventions.10252 The default depends on the specific target configuration. Note that the hard-float and soft-float ABIs are10253 not link-compatible; you must compile your entire program with the same ABI, and link with a compatible set10254 of libraries.10255 -mgeneral-regs-only10256 Generate code which uses only the general-purpose registers. This will prevent the compiler from using10257 floating-point and Advanced SIMD registers but will not impose any restrictions on the assembler.10258 -mlittle-endian10259 Generate code for a processor running in little-endian mode. This is the default for all standard10260 configurations.10261 -mbig-endian10262 Generate code for a processor running in big-endian mode; the default is to compile code for a little-10263 endian processor.10264 -mbe810265 -mbe3210266 When linking a big-endian image select between BE8 and BE32 formats. The option has no effect for little-10267 endian images and is ignored. The default is dependent on the selected target architecture. For ARMv6 and10268 later architectures the default is BE8, for older architectures the default is BE32. BE32 format has been10269 deprecated by ARM.10270 -march=name[+extension...]10271 This specifies the name of the target ARM architecture. GCC uses this name to determine what kind of10272 instructions it can emit when generating assembly code. This option can be used in conjunction with or10273 instead of the -mcpu= option.10274 Permissible names are: armv4t, armv5t, armv5te, armv6, armv6j, armv6k, armv6kz, armv6t2, armv6z, armv6zk,10275 armv7, armv7-a, armv7ve, armv8-a, armv8.1-a, armv8.2-a, armv8.3-a, armv8.4-a, armv8.5-a, armv8.6-a,10276 armv7-r, armv8-r, armv6-m, armv6s-m, armv7-m, armv7e-m, armv8-m.base, armv8-m.main, armv8.1-m.main, iwmmxt10277 and iwmmxt2.10278 Additionally, the following architectures, which lack support for the Thumb execution state, are recognized10279 but support is deprecated: armv4.10280 Many of the architectures support extensions. These can be added by appending +extension to the10281 architecture name. Extension options are processed in order and capabilities accumulate. An extension10282 will also enable any necessary base extensions upon which it depends. For example, the +crypto extension10283 will always enable the +simd extension. The exception to the additive construction is for extensions that10284 are prefixed with +no...: these extensions disable the specified option and any other extensions that may10285 depend on the presence of that extension.10286 For example, -march=armv7-a+simd+nofp+vfpv4 is equivalent to writing -march=armv7-a+vfpv4 since the +simd10287 option is entirely disabled by the +nofp option that follows it.10288 Most extension names are generically named, but have an effect that is dependent upon the architecture to

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